View MAX19693EXWD_9100074.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max19693 12-bit, 4.0gsps digital-to-analog convert-er (dac) enables direct digital synthesis of high- frequency and wideband signals. the dac has been optimized for wideband communications, radar, and instrumentation applications. the max19693 provides excellent spurious and noise performance and can be used for synthesis of wideband signals in the frequency range from dc to nearly 2ghz. the 4.0gsps update rate enables digital synthesis of signals with more than 1.5ghz bandwidth. the max19693 includes four 12-bit multiplexed low- voltage differential signaling (lvds) input ports, each operating at up to 1ghz in double data rate (ddr) or quad data rate (qdr) mode. the dac accepts a clock at 1/2 the dac update rate, as conversion is triggered on both rising and falling clock edges. the input data rate is 1/4 the dac update rate (1/2 the clock rate). the max19693 provides an lvds data clock output to sim- plify interfacing to fpga or asic devices. the max19693 is a current-steering dac with an inte- grated, self-calibrated 50 ? differential output termina- tion to ensure optimum dynamic performance. themax19693 operates from 3.3v and 1.8v power sup- plies and consumes 1180mw at 4.0gsps. the max19693 is specified over the extended temperature range (-40? to +85?) and is available in a compact 11mm x 11mm, 169 csbga package. applications radar waveform and lo signal synthesisdigital if generation in x-band transmitters electronic warfare arbitrary waveform generators direct digital synthesis automatic test equipment features ? 4.0gsps output update rate ? industry-leading dynamic performance sfdr* = 76dbc at f out = 400mhz sfdr* = 70dbc at f out = 800mhz wideband noise spectral density = -164dbm/hz ? low-power operation 770mw (f dac = 2000msps) 1180mw (f dac = 4000msps) ? 4:1 multiplexed lvds inputs up to 1000mwps each port ? internal 50 ? differential output termination ? input register scan mode for in-circuit continuityverification ? compact 11mm x 11mm, 169 csbga package ? evaluation kit available (order max19693evkit) * excludes f dac /2, f dac /4, and f dac /2 - f out spurs, which are specified separately. max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ________________________________________________________________ maxim integrated products 1 ordering information 19-3208; rev 1; 8/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max19693exw-d -40? to +85? 169 csbga max19693exw+d -40? to +85? 169 csbga + denotes a lead(pb)-free/rohs-compliant package. d = dry pack. max19693 bandgap reference and control loop clock divider /2, /4 dac clk 12 4:1 registered mux 12 x 2 12 x 2 12 x 2 12 x 2 2 outpoutn cal refres cref mod se so dap<11:0> dan<11:0> dbp<11:0> dbn<11:0>dcp<11:0> dcn<11:0> ddp<11:0> ddn<11:0> dataclkp dataclkn clkdiv delay clkp clkn refio fsadj dacref av clk v dd1.8 av dd3.3 gnd functional diagram downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 ? , r set = 2k ? , v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer- coupled differential output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd3.3 to gnd, dacref ....................................-0.3v to +3.9v v dd1.8 , av clk to gnd, dacref ..........................-0.3v to +2.1v refio, fsadj to gnd, dacref ........-0.3v to (av dd3.3 + 0.3v) outp, outn to gnd, dacref ..........-0.3v to (av dd3.3 + 1.0v) se, so, cref to gnd, dacref............-0.3v to (v dd1.8 + 0.3v) mod, delay, clkdiv, refres, cal to gnd, dacref ......................-0.3v to (av dd3.3 + 0.3v) clkp, clkn to gnd, dacref..............-0.3v to (av clk + 0.3v) dap0?ap11, dbp0?bp11, dcp0?cp11 to gnd, dacref.........-0.3v to (v dd1.8 + 0.3v) ddp0?dp11 to gnd, dacref............-0.3v to (v dd1.8 + 0.3v) dan0?an11, dbn0?bn11, dcn0?cn11 to gnd, dacref ........-0.3v to (v dd1.8 + 0.3v) ddn0?dn11 to gnd, dacref ...........-0.3v to (v dd1.8 + 0.3v) dataclkp, dataclkn to gnd, dacref ..............................................-0.3v to (v dd1.8 + 0.3v) dataclkp, dataclkn, so continuous current................8ma continuous power dissipation (t a = +70?) 169-pin csbga (derate 33.3mw/? above +70?) ..266 6.7mw thermal resistance ja (note 1) ...................................+18?/w operating temperature range............................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units static performance resolution 12 bits integral nonlinearity inl measured differentially ?.2 lsb differential nonlinearity dnl measured differentially ?.8 lsb offset voltage error os measured differentially, no external loadresistors -0.5 ?.1 +0.5 %fs offset drift ?0 ppm/? full-scale output current i out (note 3) 8 20 ma output-current gain error ge -4 +4 %fs internal reference -0.003 output-voltage gain drift external reference - 0.0025 db/? maximum cw output power p out differential, into 50 ? load -2.6 dbm output resistance r out differential, v cal 0.7 x av dd3.3 (note 4) 50 ? output return loss s 11 f out = 500mhz (note 5) 20 db note 1: thermal resistance based on a 4.5in x 5.5in multilayer board. downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dynamic performance (notes 5, 6) minimum clock rate f clk 10 mhz maximum clock rate f clk 2000 mhz minimum output update rate f dac 20 msps maximum output update rate f dac 4000 msps f d ac = 2000m sp s, f ou t = 200m h z, - 6d bfs -165 wideband noise spectral density nsd f d ac = 4000m sp s, f ou t = 200m h z, - 6d bfs -164 dbm/hz f out = 50mhz, -3dbfs 76 f out = 100mhz, -3dbfs 76 f out = 200mhz, -3dbfs 76 f dac = 1000msps f out = 300mhz, -3dbfs 76 f out = 200mhz, -3dbfs 73 f out = 400mhz, 0dbfs 62 69 f out = 600mhz, -3dbfs 75 f dac = 2000msps f out = 800mhz, -3dbfs 70 f out = 200mhz, -3dbfs 75 f out = 500mhz, -3dbfs 70 f out = 900mhz, -3dbfs 71 f dac = 3000msps f ou t = 1200m h z, - 3d bfs 68 f out = 200mhz, -3dbfs 75 f out = 400mhz, -6dbfs 62 69 f out = 800mhz, -3dbfs 63 spurious-free dynamic rangeover nyquist (note 7) sfdr f dac = 4000msps f ou t = 1500m h z, - 3d bfs 62 dbc f dac = 1000msps -87 f dac = 2000msps -98 f dac = 3000msps -81 f dac /4 clock spur f dac = 4000msps f out = 200mhz, 0dbfs -81 dbm f dac = 1000msps -57 f dac = 2000msps -50 f dac = 3000msps -54 f dac /2 clock spur f dac = 4000msps f out = 200mhz, 0dbfs -50 dbm f dac = 1000msps -40 f dac = 2000msps -40 f dac = 3000msps -40 f dac /2 - f out spur f dac = 4000msps f out = 400mhz, -6dbfs -40 dbc minimum output bandwidth bw -3db (note 8) 1500 mhz electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 ? , r set = 2k ? , v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer- coupled differential output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 4 _______________________________________________________________________________________ electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 ? , r set = 2k ? , v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer- coupled differential output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units f dac = 2000msps f out1 = 200mhz, -7dbfs, f out2 = 210mhz, -7dbfs -81 f dac = 2000msps f out1 = 400mhz, -7dbfs, f out2 = 410mhz, -7dbfs -82 f dac = 2000msps f out1 = 600mhz, -7dbfs, f out2 = 610mhz, -7dbfs -73 two-tone imd ttimd f dac = 4000msps f out1 = 800mhz, -7dbfs, f out2 = 810mhz, -7dbfs -62 dbc reference inter nal refer ence v ol tag e rang ev refio 1.1 1.2 1.3 v reference input compliancerange v refior 0.50 1.25 v reference input resistance r refio 10 k ? reference voltage drift tco ref -50 ppm/? analog output timing (note 9) output fall time t fall 90% to 10% 270 ps output rise time t rise 10% to 90% 270 ps settling to 0.1% 3.5 settling time t s settling to 0.025% 4.5 ns output propagation delay t pd 1.3 ns timing characteristics (note 10) data-to-clock setup time t setup referenced to rising edge of data clock 1.41 ns data-to-clock hold time t hold referenced to rising edge of data clock -0.88 ns lvds logic inputs (dap11 dap0, dan11 dan0, dbp11 dbp0, dbn11 dbn0, dcp11 dcp0, dcn11 dcn0, ddp11 ddp0, ddn11 ddn0) differential input logic-high v ih 100 mv differential input logic-low v il -100 mv common-mode voltage range v com 1.125 1.375 v differential input resistance r in 85 130 ? input capacitance c in 1.5 pf downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac _______________________________________________________________________________________ 5 electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 ? , r set = 2k ? , v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer- coupled differential output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units 3.3v cmos logic inputs (clkdiv, delay, mod) input logic-high v ih3.3 0.7 x av dd3.3 v input logic-low v il3.3 0.3 x av dd3.3 v input leakage current i in3.3 -5 +5 ? input capacitance c in3.3 3p f 1.8v cmos logic input (se) input logic-high v ih1.8 0.7 x v dd1.8 v input logic-low v il1.8 0.3 x v dd1.8 v input leakage current i in1.8 -5 +5 ? input capacitance c in1.8 3p f 1.8v cmos logic output (so) output logic-high v oh1.8 i source = 100? 0.7 x v dd1.8 v output logic-low v ol1.8 i sink = 100? 0.3 x v dd1.8 v clock inputs (clkp, clkn) f dac 3gsps 0 minimum clock input power(note 11) p clk f dac > 3gsps 9 dbm maximum clock input power p clk (note 11) 15 dbm common-mode voltage range v comclk 0.55 av clk /3 0.65 v input resistance r clk differential 100 ? input capacitance c clk 2p f data clock outputs (dataclkp, dataclkn) differential output v dclk with 100 ? differential termination ?.25 ?.35 ?.45 v output rise and fall time t r, t f with 100 ? differential termination 0.5 ns common-mode voltage range v com 1.125 1.25 1.375 v downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 6 _______________________________________________________________________________________ electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 ? , r set = 2k ? , v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer- coupled differential output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units power supplies analog supply voltage range av dd3.3 3.1 3.3 3.5 v 1.8v supply voltage range v dd1.8 1.7 1.8 1.9 v clock supply voltage range av clk 1.7 1.8 1.9 v f dac = 2000msps 106 analog supply current i avdd3.3 f dac = 4000msps 106 118 ma f dac = 2000msps 74 1.8v supply current i vdd1.8 f dac = 4000msps 148 190 ma f dac = 2000msps 157 clock supply current i avclk f dac = 4000msps 313 390 ma f dac = 2000msps 770 power dissipation p diss f dac = 4000msps f out = 100mhz, 0dbfs 1180 1435 mw note 2: all specifications are 100% tested at t a +25?. specifications at t a < +25? are guaranteed by design and characterization. note 3: nominal full-scale current i out = 32 x i ref . note 4: r out can be set to 50 ? as described in the output resistor calibration section. note 5: transformer-coupled output (figure 13, v cal > 0.7 x av dd3.3 ). note 6: clk input = +10dbm, ac-coupled sine wave. note 7: excludes f dac /2, f dac /4, and f dac /2 - f out spurs, which are specified separately. note 8: excludes sinc rolloff inherent in the dac. measured single-ended into 50 ? termination. note 9: measured differentially into a 50 ? termination resistor. note 10: guaranteed by design and characterization. note 11: transformer-coupled clock input (figure 5). downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac _______________________________________________________________________________________ 7 sfdr vs. output frequency (f dac = 1000msps) max19693 toc01 f out (mhz) sfdr (dbc) 400 300 200 100 50 60 70 80 9040 05 0 0 -3dbfs -6dbfs 0dbfs sfdr vs. output frequency (f dac = 2000msps) max19693 toc02 f out (mhz) sfdr (dbc) 800 600 400 200 50 60 70 80 9040 01 0 0 0 -3dbfs -6dbfs 0dbfs sfdr vs. output frequency (f dac = 4000msps) max19693 toc03 f out (mhz) sfdr (dbc) 1500 1000 500 50 60 70 80 9040 0 2000 -3dbfs -6dbfs 0dbfs sfdr vs. output amplitude (f dac = 1000msps, f out = 200mhz) max19693 toc04 a out (dbfs) sfdr (dbc) -3 -6 -9 -12 -15 50 60 70 80 9040 -18 0 sfdr vs. output amplitude (f dac = 2000msps, f out = 400mhz) max19693 toc05 a out (dbfs) sfdr (dbc) -3 -6 -9 -12 -15 50 60 70 80 9040 -18 0 sfdr vs. output amplitude (f dac = 4000msps, f out = 400mhz and 800mhz) max19693 toc06 a out (dbfs) sfdr (dbc) -3 -6 -9 -12 -15 50 60 70 80 9040 -18 0 800mhz 400mhz two-tone imd vs. output frequency (f dac = 1000msps) max19693 toc07 f out (mhz) two-tone imd (dbc) 300 200 50 60 70 80 9040 100 400 each tone -7dbfs each tone -13dbfs two-tone imd vs. output frequency (f dac = 2000msps) max19693 toc08 f out (mhz) two-tone imd (dbc) 700 600 500 400 300 200 50 60 70 80 9040 100 800 each tone -7dbfs each tone -13dbfs two-tone imd vs. output frequency (f dac = 4000msps) max19693 toc09 f out (mhz) two-tone imd (dbc) 1350 1100 850 600 350 50 60 70 80 9040 100 1600 each tone -7dbfs each tone -13dbfs typical operating characteristics (av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 510 ? , r set = 2k ? , p clk = +10dbm, v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer-coupled differential output (figure 13), i out = 20ma, t a = +25?, unless otherwise noted.) downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 8 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 510 ? , r set = 2k ? , p clk = +10dbm, v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer-coupled differential output (figure 13), i out = 20ma, t a = +25?, unless otherwise noted.) clock feedthrough vs. dac update rate (f out = 200mhz, a out = 0dbfs) max19693 toc10 f dac (msps) power (dbm) 3500 3000 2500 2000 1500 1000 -95 -70 -45 -20 -120 500 4000 f clk feedthrough f clk /2 feedthrough output noise density vs. dac update rate (f out = 200mhz) max19693 toc11 f dac (msps) output noise density (dbm/hz) 3500 3000 2500 2000 1500 -170 -165 -160 -150-155 -175 4000 -12dbfs 0dbfs -6dbfs output power vs. output frequency (a out = 0dbfs) max19693 toc12 f out (mhz) output power (dbm) 1500 1000 500 -10 -8 -6 -4 -2 -12 0 2000 1000msps 2000msps 4000msps sfdr spectral plot (f dac = 1000msps, f out = 209mhz, a out = -3dbfs) max19693 toc13 center = 250mhz, span = 500mhz, rbw = 5khz output power (dbm) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 hd2 hd3 f out f dac /2 - f out sfdr spectral plot (f dac = 2000msps, f out = 209mhz, a out = -3dbfs) max19693 toc14 center = 500mhz, span = 1ghz, rbw = 5khz output power (dbm) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 hd3 f out f dac /2 - f out sfdr spectral plot (f dac = 4000msps, f out = 425mhz, a out = -3dbfs) max19693 toc15 center = 1ghz, span = 2ghz, rbw = 10khz output power (dbm) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 hd3 f out f dac /2 - f out two-tone imd spectral plot (f dac = 1000msps, f 1 = 204mhz and f 2 = 214mhz, a out = -3dbfs) max19693 toc16 center = 209mhz, span = 40mhz, rbw = 1khz output power (dbm) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 -110 two-tone imd spectral plot (f dac = 2000msps, f 1 = 395mhz and f 2 = 405mhz, a out = -3dbfs) max19693 toc17 center = 400mhz, span = 40mhz, rbw = 1khz output power (dbm) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 -110 two-tone imd spectral plot (f dac = 4000msps, f 1 = 795mhz and f 2 = 805mhz, a out = -3dbfs) max19693 toc18 center = 800mhz, span = 40mhz, rbw = 1khz output power (dbm) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 -110 2f 1 - f 2 2f 2 - f 1 f 1 = 795mhz f 2 = 805mhz downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac _______________________________________________________________________________________ 9 sfdr vs. temperature (f dac = 2000msps, f out = 200mhz) max19693 toc19 temperature ( c) sfdr (dbc) 60 35 10 -15 50 60 70 80 9040 -40 85 -3dbfs -6dbfs 0dbfs sfdr vs. temperature (f dac = 4000msps, f out = 400mhz) max19693 toc20 temperature ( c) sfdr (dbc) 60 35 10 -15 50 60 70 80 9040 -40 85 -3dbfs 0dbfs -6dbfs two-tone imd vs. temperature (f dac = 4000msps, f out = 400mhz) max19693 toc21 temperature ( c) two-tone imd (dbc) 60 35 10 -15 50 60 70 80 9040 -40 85 each tone -9dbfs each tone -12dbfs f clk /2 - f out spur vs. output frequency (a out = 0dbfs, clkdiv = 0) max19693 toc22 f out (mhz) power (dbm) 800 600 400 200 -45 -40 -35 -30 -25 -20-50 0 1000 2400msps 3500msps internal reference (refio) voltage vs. temperature max19693 toc23 t a ( c) v refio (v) 60 35 10 -15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.251.15 -40 85 integral nonlinearity vs. digital output code max19693 toc24 digital output code inl (lsb) 3072 4095 2048 1024 0 21 -1-2 0 differential nonlinearity vs. digital output code max19693 toc25 digital output code dnl (lsb) 3072 4095 2048 1024 10 -1 0 supply current vs. clk frequency (f out = 100mhz, a out = 0dbfs) max19693 toc26 f clk (mhz) supply current (ma) 1700 1400 1100 800 100 200 300 400 500 0 500 2000 3.3v (av dd3.3 ) 1.8v (v dd1.8 + av clk ) typical operating characteristics (continued) (av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 510 ? , r set = 2k ? , p clk = +10dbm, v refio = external 1.25v, v cal = 3.3v, v mod = 0v, transformer-coupled differential output (figure 13), i out = 20ma, t a = +25?, unless otherwise noted.) downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 10 ______________________________________________________________________________________ pin description pin name function a1 refio refer ence inp ut/o utp ut. inter nal 1.2v b and g ap r efer ence outp ut. re fio has a 10k ? ser i es r esi stance and can b e d r i ven usi ng an exter nal r efer ence. c onnect a 1? cap aci tor b etw een re fio and d ac re f. a2 fsadj full-scale adjust input. sets the full-scale output current of the dac. to obtain a 20ma full-scaleoutput current using the internal reference, connect a 1.92k ? resistor between fsadj and dacref. a3 dacref current-set resistor return path. to obtain a 20ma full-scale output current using the internalreference, connect a 1.92k ? resistor between fsadj and dacref. dacref is internally connected to agnd. do not connect dacref to external ground. a4, a5, a7, a9 av dd3.3 analog 3.3v supply voltage. accepts a 3.1v to 3.5v supply voltage range. connect 0.047? bypass capacitors between each av dd3.3 node and gnd. a6 outp p osi ti ve ter m i nal of d i ffer enti al d ac o utp ut. an i nter nal cal i b r ated 25 ? r esi stor connects ou tp to av d d 3 .3 . a8 outn n eg ati ve term i nal of d i ffer enti al d ac outp ut. an i nter nal cal i b r ated 25 ? r esi stor connects ou tn to av d d 3.3 . a10, b10, c2, c3, c10, e1?4, e10?13, f13 v dd1.8 analog 1.8v supply voltage. accepts a 1.7v to 1.9v supply voltage range. connect 0.047? bypass capacitors between each v dd1.8 node and gnd. a11, a13, b5?9, b11, c4?9, c11, d1?11, d13, e5?9, g13 gnd ground. connect gnd to the ground plane with minimum inductance. a12, b12, c12, d12 av clk clock 1.8v supply voltage. accepts a 1.7v to 1.9v supply voltage range. connect 0.047? bypasscapacitors between each av clk node and gnd. b1 cref noise bypass node. a 1? capacitor between cref and dacref band limits the phase noise. b2 refres calibration reference resistor input. connect a 510 ? resistor between refres and av dd3.3 . the internal analog output resistors are calibrated to this external resistor. b3 n.c. no connection. leave unconnected, or connect to ground. b4 mod f dac /2 or f clk modulation control input. mod = 1: modulation onmod = 0: modulation off mod is a 3.3v cmos input with an internal pulldown resistor. c13 clkp converter clock positive input. an internal 100 ? termination resistor connects clkp to clkn. b13 clkn converter clock negative input. an internal 100 ? termination resistor connects clkp to clkn. c1 cal dac output resistance calibration input.calibration of the internal output resistors is initiated by a rising edge on cal. cal = 1: output resistor calibration is held cal = 0: output resistors are uncalibrated cal is a 3.3v cmos input with an internal pulldown resistor. the clock must be operating to calibrate and to hold calibration. leakage current is less than ??. downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 11 pin description (continued) pin name function f6?3, f1, f2, h6?1 dap11 dap0 a-channel positive lvds data inputs. dap11 is the msb. input coding in offset binary format. g6?3, g1, g2, j6?1 dan11 dan0 a-channel negative lvds data inputs k1?4, m1?4, k5, m5, k6, m6 dbp11 dbp0 b-channel positive lvds data inputs. dbp11 is the msb. input coding in offset binary format. l1?4, n1?4, l5, n5, l6, n6 dbn11 dbn0 b-channel negative lvds data inputs m7, k7, m8, k8, m9?12, k9, k10, k11, l12 dcp11 dcp0 c-channel positive lvds data inputs. dcp11 is the msb. input coding in offset binary format. n7, l7, n8, l8, n9?12, l9, l10, l11, k12 dcn11 dcn0 c-channel negative lvds data inputs g7, j7, j12?8, g12?8 ddp11 ddp0 d-channel positive lvds data inputs. ddp11 is the msb. input coding in offset binary format. f7, h7, h12?8, f12?8 ddn11 ddn0 d-channel negative lvds data inputs j13 dataclkp lvds data clock positive output h13 dataclkn lvds data clock negative output k13 delay data clock delay mode input.adjusts the delay of the output data clock. delay = 0: no delay added delay = 1: add delay of 1/2 input data period (one dac clock cycle) delay is a 3.3v cmos input with an internal pulldown resistor. l13 clkdiv data clock divide mode input.clkdiv = 1: (ddr mode) data clock rate = input data rate/2 (f clk /4) clkdiv = 0: (qdr mode) data clock rate = input data rate/4 (f clk /8) clkdiv is a 3.3v cmos input with an internal pulldown resistor. m13 se scan enable input. se is a 1.8v cmos logic input. during normal operation, se is internally connected to gnd. when se is high (1.8v), the parallel input register is configured as a shift register, allowing the contents of the input register to be shifted out on the scan output (so). n13 so scan output. so is a 1.8v cmos logic output and active when scan enable (se) is high. downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 12 ______________________________________________________________________________________ detailed description the max19693 is a high-performance, high-speed, 12-bit current-steering dac with an integrated 50 ? differ- ential output termination. the dac is capable ofoperating with a clock rate (f clk ) of up to 2.0ghz. since the output is latched on both rising and fallingclock edges, a 2.0ghz clock results in a dac update rate (f dac ) of 4.0gsps. the converter consists of an edge-triggered 4:1 inputdata multiplexer followed by a current-steering circuit. this circuit is capable of generating differential full-scale currents from 8ma to 20ma. internal 25 ? resistors on each output, in combination with an external termination,convert the differential current into a voltage. the internal resistors are terminated to the 3.3v analog supply (av dd3.3 ). the internal termination resistors can be cali- brated to an external 510 ? precision resistor. a calibra- tion cycle can be run every time the converter ispowered up, or at any other time as long as the clock is operating. an integrated 1.2v bandgap reference, con- trol amplifier, and user-selectable external resistor deter- mine the data converter? full-scale range. reference input/output the max19693 supports operation with the on-chip1.2v bandgap reference or an external reference volt- age source. refio serves as the input for an external, low-impedance reference source, and as the output if the dac is operating with the internal reference. for stable operation with the internal reference, decouple refio to dacref with a 1? capacitor. since refio has a 10k ? series resistance, buffer refio with an external amplifier to drive external loads.the max19693? reference circuit (figure 1) employs a control amplifier designed to regulate the full-scale cur- rent (i out ) for the differential current outputs of the dac. the output current can be calculated as follows: i out = 32 x i ref x 4095/4096 where i ref is the reference output current (i ref = v refio /r set ) and i out is the full-scale output current of the dac. located between fsadj and dacref, r set is typically set to 1.92k ? , resulting in a full-scale current of 20ma and a maximum of -2.6dbm output power for acw signal if the internal reference is used. generally, the dynamic performance of the dac improves with increasing full-scale current. refio can be driven by an externally applied refer- ence voltage for gain adjustment/level-control purpos- es. the bandwidth of the control amplifier in figure 1 is typically less than 100khz, and the input resistance at refio is 10k ? . analog outputs the max19693 is a differential current-steering dacwith built-in, self-calibrated output-termination resistors to optimize performance. the outputs are terminated to av dd3.3 , and are calibrated to provide a 50 ? differen- tial output resistance. in addition to the signal current, aconstant 10ma current sink is connected to each dac output. typically, the outputs are used with a 50 ? balun transformer. if the transformer is center-tapped, it isrecommended that the center tap be connected to av dd3.3 . if the transformer is not center-tapped, induc- tors can be used to pull up the outputs, as shown infigure 13. figure 2 shows an equivalent circuit of the internal output structure of the max19693. r set i ref = v refio /r set refio fsadj dacref outp outn current- source array dac 10k ? max19693 1.2v reference i ref 1 f figure 1. reference architecture, internal reference configuration downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 13 the output termination resistors (r t ) are calibrated to 23.5 ? . r m (r m1 + r m2 + r m3 ) is the resistance of the dac output traces and bond wires, and is not calibrat-ed. the output resistance is equal to 2r t + 2r m , and is nominally 50 ? . the max19693 is normally used with an external differential 50 ? load (r l ). for this case, the peak differential output voltage is calculated as follows: v out = i out x r l r t /(r l + 2 r m + 2 r t ) where i out is the full-scale current, typically set to 20ma. with r l = 50 ? , r t = 23.5 ? , and r m = 1.5 ? , v out is 0.235v. this corresponds to an output power of -2.6dbm. as shown in figure 2, the output circuit hassome resistive, capacitive, and inductive elements. these elements limit the output bandwidth to 1.5ghz with a resistive differential load of 50 ? . output resistor calibration the integrated termination resistor (r t ) must be cali- brated to have an accurately known dac output resis-tance and voltage. the termination resistors are calibrated to the external reference resistor (r refres ) connected between refres and av dd3.3 . r refres is nominally 500 ? . a plot showing the typical relation between the dac output resistance and r refres is shown in figure 3. the calibration cycle is initiated with a rising edge oncal. while the clock is running, cal must be asserted and held high after the supply voltages and the refer- ence voltage have reached steady state. input data should not be switching while the calibration is running. the duration of the calibration cycle is shorter than 65,536 dac clock cycles (less than 32.8? if the con- verter is operated with a 2ghz clock rate). cal must be held high for the output resistors to remain calibrat- ed. if the clock is stopped, or if power is cycled, a new calibration cycle must run. 44 4746 45 4948 5150 52 5453 55 450 470 480 490 460 500 510 520 540 530 550 r refres ( ? ) r out ( ? ) figure 3. output resistance vs. refres resistor av dd3.3 r t = 23.5 ? r t = 23.5 ? r m1 = 0.6 ? r m2 = 0.4 ? r m3 = 0.5 ? r m1 = 0.6 ? r m2 = 0.4 ? r m3 = 0.5 ? 50 ? 3pf 3pf 0.75pf 0.4pf 0.4pf 0.5pf outn outp 0.5pf 0.3nh 0.3nh 0.3nh 0.3nh 1.3nh1.3nh 10ma + i out x (4095 - code)/4096 10ma + i out x code/4096 figure 2. equivalent output circuit downloaded from: http:///
clock inputs the max19693 features a flexible differential clockinput (clkp, clkn) operating from a separate supply (av clk ) to achieve the best possible jitter performance. the two clock inputs can be driven from a single-endedor a differential clock source. a sine wave or a square wave can be used. for single-ended operation, drive clkp with a logic source, and bypass clkn to gnd with a 0.1? capacitor. driving the clocks differentially is recommended for optimum jitter performance. choose a clock amplitude that is as large as possible (without the clock voltage at the clkn and clkp going more than 300mv below ground or above the av clk supply voltage) to minimize jitter. for an ac-coupled, differential sine-wave clock,using the input circuit of figure 4 or 5, clock power should not be higher than 15dbm. the max19693 can be used with a sinusoidal clock ampli- tude as low as 0.6v p-p (0dbm) below 3gsps. for higher update rates, a clock amplitude between 10dbm and12dbm is recommended for optimum noise performance. the clkp and clkn are internally biased to 0.6v withresistors. this allows ac-coupling of clock sources directly to the device without external resistors to define the dc level. an internal 100 ? termination resistor connects clkp to clkn. add an external 100 ? termination resistor when using a 50 ? clock source. see figure 4 for a conve- nient way to apply a differential signal created from asingle-ended source and a wideband transformer. the clock circuit in figure 4 provides amplitude asym- metry at update rates above 3gsps due to transformer loss, which may cause the clock duty cycle to deviate from 50% for clock rates close to 2ghz. this may cause the image spur at f dac /2 - f out to increase by several decibels (db). figure 5 shows a clock interfacecircuit with improved symmetry using three balun trans- formers. this clock interface circuit provides symmetric and balanced clock signals for frequencies up to the maximum update rate of the max19693. an equivalent circuit model for the clock inputs is shown in figure 6. max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 14 ______________________________________________________________________________________ 100nf100nf mini-circuits tc1-1-13m 50 ? 50 ? 100 ? 5k ? 5k ? +0.6v max19693 clkpclkn figure 4. typical clock application circuit single-ended clock input mini-circuits tc1-1-13m mini-circuits tc1-1-13m mini-circuits tc1-1-13m 50 ? 50 ? 100pf clkp clkn 100pf figure 5. clock application circuit with improved symmetry 0.1 ? 100 ? 5k ? 5k ? 10k ? 5k ? 100 ? 100 ? 0.1pf 0.1pf 1pf 0.05pf clkp clkn 0.1pf 0.1pf 2.7nh av clk 0.1 ? 1pf 2.7nh figure 6. clock input equivalent circuit downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 15 clock duty cycle the dac output is updated on both the rising andfalling clock edges. use a clock with a duty cycle as close to 50% as possible. when using an ac-coupled sine-wave clock, the clock duty cycle is automatically close to 50%. deviation from a balanced duty cycle contributes to an image in the output spectrum. the magnitude of the image is dependent on the deviation from an ideal 50% duty cycle. this artifact occurs at the following frequency: another artifact resulting from updating the dac output on both edges is the generation of a spur at the clock frequency, or 1/2 the dac update rate. note that this spur is not related to the duty cycle: f dac /2 modulation (mod) the max19693 mod input (b4 node) provides f dac /2 (or f clk ) modulation as shown in figure 7 when it is set to logic 1. mod is a 3.3v cmos logic input pin. settingmod to logic-high inverts data on ports b and d inside the max19693. using the mod function improves imd when synthesiz- ing some high-frequency signals. to use the mod function, set mod to logic-high and invert data on ports b and d. data inputs data inputs (dap[11:0], dan[11:0], dbp[11:0],dbn[11:0], dcp[11:0], dcn[11:0], ddp[11:0], ddn[11:0]) are lvds receivers followed by edge- triggered flip-flops. four 12-bit buses accept data in offset binary format. the lvds inputs feature on-chip termination with differential 100 ? resistors. a 1.25v common-mode level with a standard lvds differentialswing can be applied to these inputs. see figure 8 for an equivalent circuit of the lvds inputs. f f spur dac = 2 f f f image dac out = 2 dac inputdac input dac outputdac output mod = 0 f dac /2 or f clk f in f in f dac or 2 x f clk f dac - f in f in f dac - f in f dac - f in f dac /2 - f in f dac /2 + f in f dac or 2 x f clk f dac or 2 x f clk f dac or 2 x f clk f dac /2 or f clk f dac /2 or f clk f dac /2 or f clk mod = 1 figure 7. f dac /2 modulation using the mod input downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 16 ______________________________________________________________________________________ data timing relationships the timing of the lvds inputs is defined with respect tothe lvds output dataclk (dataclkp, dataclkn). the lvds data inputs are latched at 1/2 the input clock frequency. the dataclk output frequency is divided by another factor of 4 (clkdiv = 0) or by 2 (clkdiv = 1). define the 0 point of dataclk as the rising edge. for the case of clkdiv = 1, data is latched at 0 and 180 of dataclk, and setup and hold times must be satisfied for both these points in time. for the case of clkdiv = 0, data is latched at 0? 90? 180? and 270 of dataclk. setup and hold times must be satisfied for all four of these points in time. the delay input can skew dataclk by 1/2 of the input data period, as shown in figure 9. this eases interfacing to fpgas where the clock to q delay of the lvds outputs is not adjustable. the clock driving the data input register is not delayed with delay. the setup and hold times are always referred to the case when delay = 0. data-timing relationships are shown in figure 10. d_p d_n 0.05 ? 0.05 ? 1.2nh1.2nh 0.1 ? 106 ? 0.1 ? 0.03pf 1.2pf 1.2pf 1.75nh1.75nh k = 0.25 coupling factor k = 0.47 coupling factor d to 4:1 multiplexer q clk clock figure 8. lvds input equivalent circuit 0ns 0.5ns 2.0ns clkp, clkn 2ghz dataclk = 500mhz (delay = 0) clkdiv = 1 dataclk = 500mhz (delay = 1) clkdiv = 1 dataclk = 250mhz (delay = 0) clkdiv = 0 dataclk = 250mhz (delay = 1) clkdiv = 0 4.0ns 1.0ns 1.5ns 2.0ns 2.5ns 3.0ns 3.5ns 4.0ns 4.5ns 5.0ns 5.5ns 6.0ns 6.5ns 7.0ns figure 9. effect of delay input on data clock output downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 17 0ns 0.5ns 1.0ns 1.5ns 2.0ns 2.5ns 3.0ns 3.5ns 4.0ns 4.5ns 5.0ns 5.5ns 6.0ns 6.5ns 7.0ns 2.0ns t h clkp, clkn 2ghz dataclk 500mhz data 1ghz clkp, clkn 2ghz dataclk 250mhz data 1ghz t s 4.0ns max19693 1ghz ddr mode max19693 1ghz qdr mode t h t s t h t s t h t s t h t s t h t s t h t s t h t s t h t s t h t s figure 10. setup (t s ) and hold time (t h ) for data input interface data inputs da<11:0>, db<11:0>, dc<11:0>, dd<11:0> data outputs qa<11:0>, qb<11:0>, qc<11:0>, qd<11:0> (a) input register (se = 0) (b) input register (se = 1) dq dq dq dq dq dq dq dq dq dq gnd qa11 qa10 qa9 qd3 qd2 qd1 qd0 so figure 11. input register flip flops in normal operation (a) and scan mode (b) downloaded from: http:///
input register scan the outputs of the data input register on the max19693can be monitored on the so (scan output) pin to allow verification of the connectivity of the data input pins. this function is enabled using the se (scan enable) pin. when se is logic 0 (0v), the input register operates nor- mally, and so is in a high-impedance state. when se is logic 1 (1.8v), the input register flip-flops are reconfig- ured to be a 48-bit shift register, connected to the so output as shown in figure 11. data is clocked out at the input register data rate. a timing diagram for the operation is shown in figure 12. known input data is applied to the dac data inputs on the first dataclk pulse, and the input register is loaded in a parallel fashion. note that the input data needs one clock cycle to propagate before se can be set to logic 1. when se is set to logic 1, the input register is config- ured as a 48-bit long shift register, outputting at so. the order of the bit output on so is qd<0:11>, qc<0:11>, qb<0:11>, and qa<0:11>, followed by constant low until se is set low, which brings so into high- imped- ance mode again. the scan interface is a 1.8v cmos logic interface. applications information differential coupling using rf transformers the differential voltage between outp and outn canbe converted to a single-ended voltage using a trans- former or a differential amplifier configuration. using a differential transformer-coupled output (cw output power is limited to -2.6dbm) optimizes the dynamic per- formance. use bias tees built from discrete inductors and capacitors (figure 13) for optimal performance.pull up the dac outputs to 3.3v. not pulling up the out- puts to 3.3v may result in some degradation of dynamic performance if the full-scale current is set to 20ma. a recommended output circuit is shown in figure 13. to achieve the maximum bandwidth, minimize the induc- tance in the ground lead on the secondary side of the transformer. use a very short trace and multiple vias for the connection to the ground plane. alternatively, the dac output can be ac-coupled into a wideband differ- ential amplifier. max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 18 ______________________________________________________________________________________ dataclk se so input data qd0 qd1 qd2 qd3 qd4 qd5 qb8 qb9 qa11 0 0 figure 12. timing diagram, scan operation 50 ? single-endedoutput mini-circuits tc1-1-13m coilcraft 1008cs-391 av dd3.3 coilcraft 1008cs-391 av dd3.3 outp outn max19693 0.01 f 0.01 f 0.39 h 0.39 h figure 13. differential to single-ended conversion circuit for max19693 analog output downloaded from: http:///
data synchronization the dac clock runs at twice the data rate of the datainterface to the max19693. an lvds level data clock output (dataclkp, dataclkn) helps to synchronize the data source and the dac. the output data clock frequency can be set to 1/2 the input data rate or 1/4 the input data rate. when the dac is operating at full speed, this allows the data clock to be interfaced directly to fpgas without using an external clock divider. for example, if the dac is updating at 4gsps, the input data rate is 1gwps. if the dac is interfaced to an fpga, the data clock can operate at 1/4 the data input rate; hence the data output clock frequency would be 250mhz. if the system clock is operating at the dac clock rate, the scheme in figure 14(a) can be used. in this case, the system is clocked using the data clock output from the dac. the delays of the data and the clock depend upon line lengths and loading. hence, clock deskewing using a phase-locked loop ordelay-locked loop may be necessary to make this sys- tem work properly at high frequencies. when clkdiv = 0, the data clock output can be phase-shifted by 45 using delay. when clkdiv = 1, the data clock output can be phase-shifted by 90 using delay. an alternative solution is shown in figure 14(b). in this case, the system clock distribution is running at the data clock rate. a low-jitter, low-phase-noise phase- locked loop is used to generate the high-speed dac clock. using the data clock for feedback into the pll ensures synchronization between data and clock. if more than one max19693 is used in a system, and the relative phases need to be defined, the divided data clock of each dac should be phase locked to a system clock running at data rate/4 or data rate/2, equal to the dac clock rate divided by 8 or 4, respectively. max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 19 max19693 dac out output register data source (fpga/asic) dataclk 4:1 mux (a) lvds data f clk /n* f clk (b) f clk /n* *n = 4 or n = 8 as set by clkdiv system clock f clk /n* output register data source (fpga/asic) max19693 dac out dataclk 4:1 mux low-phase-noise pll phase det vco figure 14. data source to dac interfacing downloaded from: http:///
grounding, bypassing, power-supply, and board-layout considerations grounding and power-supply decoupling can stronglyinfluence the performance of the max19693. unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, affecting dynamic performance. proper grounding and power- supply-decoupling guidelines for high-speed, high- frequency applications should be closely followed. this reduces emi and internal crosstalk that can significantly affect the dynamic performance of the max19693. use of a multilayer pcb with separate ground and power-supply planes is required. it is recommended that the analog output and the clock input are run as controlled-impedance microstrip lines on the top layer of the board, directly above a ground plane, and that no vias are used for the clock input (clkp, clkn) and the analog output (outp, outn) signals. depending on the length of the traces, and the operating condition, a low-loss dielectric material (such as rogers ro4003) as the top layer dielectric may be advisable. the data clock (dataclkp, dataclkn) must be rout- ed so coupling into the clock input and the dac output is minimized. digital input signals should be run as controlled- impedance strip lines between ground planes. digital signals should be kept as far away from sensitive analog inputs, reference input sense lines, common- mode inputs, and clock inputs as practical. it is partic- ularly important to minimize coupling between digital signals and the clock, to optimize dynamic perfor- mance for high output frequencies. a symmetric design of the clock input and analog output lines is critical to minimize distortion and optimize the dac? dynamic performance. digital signal paths should be kept short and run lengths matched to avoid data-delay mismatch. the max19693 supports three separate power-supply inputs for analog 3.3v (av dd3.3 ), switching (v dd1.8 ), and clock (av clk ) circuits. each av dd3.3 , v dd1.8 , and av clk input should at least be decoupled with a sepa- rate 0.047? capacitor as close as possible to the input,and their opposite ends with the shortest possible con- nection to the corresponding ground plane to minimize loop inductance. all three power-supply voltages should also be decoupled at the point they enter the pcb with tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitorsforming a pi-network could also improve performance. the power-supply inputs (v dd1.8 and av clk ) of the max19693 allow a 1.8v ?.1v supply voltage range.the analog power-supply input (av dd3.3 ) allows a 3.3v ?.2v supply voltage range. to optimize the dynamicperformance of the max19693 over temperature at the highest update rates, it is important that the difference between v dd1.8 and av dd3.3 is at least 1.4v. if v dd1.8 is 1.9v and av dd3.3 is 3.1v, dynamic performance at these update rates degrades at higher temperatures.the max19693 is packaged in a 169 csbga with 0.8mm ball pitch (package code: x16911-1) , providing design flexibility, thermal efficiency, and a small foot-print for the dac. static performance parameter definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transferfunction from either a best straight-line fit (closest approximation to the actual transfer curve) or end-point fit (a line drawn between the end points of the transfer function, once offset and gain errors have been nullified). for a dac, the deviations are measured at every individ- ual step. the max19693 inl is specified using the end- point method. differential nonlinearity (dnl) dnl is the difference between an actual step heightand the ideal value of 1 lsb. a dnl error specification greater than -1 lsb guarantees a monotonic transfer function. offset error the offset error is the difference between the ideal and theactual offset current. for a differential output dac, the off- set point is the average value at the output for the two mid- scale digital input codes with respect to the full scale of the dac. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and theactual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percent- age error in each step. max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 20 ______________________________________________________________________________________ downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 21 dynamic performance parameter definitions settling time the settling time is the amount of time required from thestart of a transition until the dac output settles to its new output value to within the specified accuracy. noise spectral density the dac output noise is the sum of the quantization noiseand other noise sources. noise spectral density is the noise power in a 1hz bandwidth. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the carrier fre-quency (maximum signal components) to the rms value of the largest distortion component. sfdr is usually mea- sured in dbc with respect to the carrier frequency ampli- tude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-/four-tone intermodulation distortion (imd) the two-/four-tone imd is the ratio, expressed in dbc ordbfs, of the worst 3rd-order or higher imd products to any output tone. downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac 22 ______________________________________________________________________________________ max19693 1 234 56 7891 01 11 21 3 fsadj dacref av dd3.3 refio top view a1 f1 e1 d1 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 ab c d cref refres n.c. mod gnd cal v dd1.8 v dd1.8 gnd gnd gnd gnd gnd e f v dd1.8 v dd1.8 v dd1.8 v dd1.8 dap7 dap6 dap8 dap9 av dd3.3 outp gnd gnd gnd gnd gnd gnd dap10 dap11 g h j dan7 dan6 dan8 dan9 dan10 dap0 dap1 dap2 dap3 dan0 dan1 dan2 dan3 k l dbp11 dbp10 dbp9 dbp8 dbn11 dbn10 dbn9 dbn8 dan11 dap4 dap5 dan4 dan5 dbp3 dbp1 dbn3 dbn1 m n dbp7 dbp6 dbp5 dbp4 dbp2 dbn7 dbn6 dbn5 dbn4 dbp0 dbn2 dbn0 av dd3.3 outn av dd3.3 gnd gnd gnd v dd1.8 gnd gnd gnd gnd gnd gnd gnd gnd gnd ddn11 ddn0 ddn1 v dd1.8 gnd v dd1.8 gnd gnd gnd v dd1.8 v dd1.8 ddn2 ddn3 ddp11 ddp0 ddp1 ddp2 ddn10 ddn5 ddn6 ddp10 ddp5 ddp6 dcp10 dcp8 dcp3 dcn10 dcn8 dcn3 ddp3 ddn7 ddn8 ddp7 ddp8 dcp2 dcp1 dcn2 dcn1 dcp11 dcp9 dcp7 dcp6 dcn11 dcn9 dcn7 dcp5 dcn6 dcn5 av clk av clk clkn av clk av clk v dd1.8 ddn4 gnd gnd gnd clkp gnd v dd1.8 v dd1.8 ddp4 gnd ddn9 ddp9 dcn0 dcp0 dataclkn dataclkp delay clkdiv dcp4 se dcn4 so pin configuration the max19693 is packaged in a compact 11mm x 11mm, 169 csbga (package code x16911-1 (leaded) or x16911+1 (lead-free)). ball pitch is 0.8mm. downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac ______________________________________________________________________________________ 23 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to th e package regardless of rohs status. package type package code outline no. land pattern no. 169 csbga x16911+1 21-0165 90-0186 downloaded from: http:///
max19693 12-bit, 4.0gsps high-dynamic performance wideband dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/08 initial release 1 8/10 add lead-free package, update absolute maximum ratings 1, 2, 22, 23 downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX19693EXWD

	To Download MAX19693EXWD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .